1. Field of the Invention
Embodiments of the invention relate to internal wiring structures of semiconductor devices such as, but not limited to, power semiconductor modules.
2. Related Art
FIG. 8 is a substantial cross-sectional view schematically showing a conventional power semiconductor module. This power semiconductor module 500 configures a three-phase inverter circuit in which six semiconductor chips 55 made up of IGBT chips 55a and FWD chips 55b are stored in a resin case. FIG. 8 is a substantial cross-sectional view that schematically shows one of the IGBT chips 55a and one of the FWD chips 55b. The IGBT chip 55a and the FWD chip 55b are connected to each other by bonding wires 56c. A flat plate such as a copper plate, for example, is used as each wiring conductor 56 that connects a conductive pattern of an insulating substrate 53 with a conductive pattern and an external lead terminal 57 to each other. The detail of this configuration is described hereinafter.
This power semiconductor module 500 includes a heat dissipation base 51, the insulating substrate 53 with a conductive pattern, a rear conductive film of which adheres to the heat dissipation base 51 via a solder 52, and the semiconductor chips 55 such as the IGBT chip 55a and the FWD chip 55b adhering to a front conductive pattern of the insulating substrate 53 with a conductive pattern via a solder 54.
The power semiconductor module 500 also includes the bonding wires 56c that connect the semiconductor chips 55 to each other, the bonding wires 56c that connect the semiconductor chips 55 and the conductive patterns to each other, the wiring conductors 56 having one end adhering to the conductive pattern of the insulating substrate 53 with a conductive pattern, the external lead terminal 57 to which the other end of the wiring conductors 56 is connected, a resin case 58 to which the external lead terminal 57 adheres and which adheres to an outer circumference of the heat dissipation base 51, and gel 59 for filling the resin case 58.
Due to the three-phase inverter circuit configured in the power semiconductor module 500, the wiring conductors 56 are disposed inside the resin case 58, in the form of flat plates, such as copper plates, with a P-terminal wire, an N-terminal wire, a U-terminal wire, a V-terminal wire, and a W-terminal wire.
In the internal wiring structure of the power semiconductor module 500, the copper plates configuring the wiring conductors 56 having the above-mentioned terminal wires are disposed so as to partially oppose each other and be partially parallel to each other. Thus, in some sections of the wiring conductors 56, currents flow in the same direction (e.g., a section A).
FIG. 9 is a substantial perspective view showing the section (section A) with first and second wiring conductors 56a and 56b where a current 60a (solid arrow) and a current 60b (dashed arrow) flow in the same direction, the first and second wiring conductors 56a and 56b being disposed so as to oppose each other and in parallel to each other. A wiring inductance L of the first and second wiring conductors 56a and 56b at this section is a sum of a self inductance Ls and a mutual inductance M; L=Ls±M. The symbol “+” means that the directions of the currents flowing in the parallel wiring conductors 56a, 56b are the same, whereas the symbol “−” means that the directions of the currents are opposite to each other.Ls=(μT/2π)×(log(2T/a)−(¾))M=(μT/2π)×(log(2T/d)−(¾))
where “T” represents the length of the wiring conductors, “a” the radius of the wiring conductors (when the wiring conductors have a circular cross-section) (in FIG. 9, the radius is obtained by converting the cross-sectional area to equivalent round), “μ” the magnetic permeability of the wiring conductors, and “d” the distance between central axes of the wiring conductors.
In the section described above, the mutual inductance M increases, and the wiring inductance L of the wiring conductors 56a, 56b also increases.
In addition, in Japanese Patent Application Publication No. 2006-60986 (also referred to herein as “Patent Document 1”), a slit (notch) is formed on a side surface of a conventional single straight wiring conductor to allow the current flowing through the single wiring conductor to meander through, so that a high-frequency resistance of the single wiring conductor increases, further reducing radiation noise. With this structure, radiation noise caused by a switching operation of a semiconductor element (semiconductor chip) such as an IGBT can be reduced without particularly increasing the size of a circuit or a device. Another example where a skin effect is used in place of the slit is described in Patent Document 1.
Patent Document 1 describes that the formation of a slit for reversing the direction of the current flowing through the single wiring conductor can reduce the radiation noise.
Japanese Patent Application Publication No. 2009-64852 (also referred to herein as “Patent Document 2”) discloses a power semiconductor module 600 shown in FIG. 10 in which a rear conductive film 72 made from a metal foil is formed on a first main surface of an insulating plate 71 and at least one conductive pattern 73 made from another metal foil is formed on a second main surface of the insulating plate 71. Furthermore, the power semiconductor module 600 has a printed board 75 that is disposed so as to face (at least one) semiconductor chip 74, which is a semiconductor element bonded onto the latter metal foil, and so as to face a main surface of the insulating plate 71 in which the semiconductor element is disposed. A wiring conductor 76, which is a metal foil formed on a first main surface (front side) of the printed board 75, or another wiring conductor 77, which is a metal foil formed on a second main surface (rear side) of the printed board 75, is electrically connected to a main electrode of the semiconductor element by a plurality of post electrodes 78. The wiring conductors 76, 77 are configured as two layers of metal foils in which currents flow in the same direction. According to Patent Document 2, having such a configuration, a semiconductor device that provides high contact reliability, excellent operating characteristics, and high productivity can be realized.
In the configuration described above, currents constantly flow in the same direction in the wiring conductors 76, 77 which are the metal foils having the printed board 75 therebetween.
When the semiconductor chips 55, 74 are turned ON/OFF with the increased wiring inductance L described above, a large surge voltage (−L (di/dt)) is applied to the semiconductor chips 55, 74, causing damage to the semiconductor chips 55, 74, increasing magnetic noise, and causing other errors. In addition, high switching loss is produced, increasing the amount of heat generated in the semiconductor chips 55, 74.
FIG. 11 is a schematic perspective view of two wiring conductors that are disposed so as to oppose each other and in parallel to each other. For example, when the wiring conductors 56a, 56b has a length T of 5 mm, a width W1 of 1 mm, a thickness W2 of 0.18 mm, a gap t of 0.05 mm, the mutual inductance M becomes as high as 2.0 nH, as shown in FIG. 12.
In Patent Document 2 mentioned above, the mutual inductance M is high because the wiring conductor 76, which is a metal foil formed on the first main surface of the printed board 75, and the wiring conductor 77, which is another metal foil formed on the second main surface of the printed board 75, are disposed so as to closely oppose each other and the currents flow in the same direction. Patent Document 2 describes that the mutual inductance M can be lowered by tangling the wiring conductors 76, 77 as shown in FIG. 18 of Patent Document 2, the wiring conductors 76, 77 being metal foils that are disposed so as to oppose each other vertically.
Thus, as described above, there are certain limitations in the related art.